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Time
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Titles
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Speakers or additional info
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9:00-9:30
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Registration
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9:30-9:40
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Welcome/Introduction
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Artur Jutman
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9:40-10:40
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Key Note Session
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Chairman: Knut Båtstoløkken
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9:40-10:40
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Is There Any Innovation Left in Test?
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Bill Eklow, Cisco Systems
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10:40-11:00
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Exhibitor presentations
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Chairman: Jürgen Sedlacek
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11:00-11:30
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Coffee Break / Exhibition
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11:30-13:00
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Session 1: Structural Test
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Chairman: Mick Austin
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11:30-12:00
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Probe design and material selection for optimal lead free board testing
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Bruce Valentine, IDI
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12:00-12:30
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Using Wave Form To Test For Opens On Component Packages
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Michael Smith, Consultant
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12:30-13:00
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Testing High-Density Electro-Optical Backplane
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Knut Båtstoløkken, Kitron
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13:00-14:00
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Lunch |
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14:00-15:30
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Session 2: Structural/Functional Test
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Chairman: Birger Schneider |
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14:00-14:30
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Laser Height Measurement Monitoring Solder and Placement of BGA, uBGA and Flip Chips
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Michael Smith, Consultant
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14:30-15:00
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Hardware In the Loop (HIL) testing is mainly used in Aerospace and Automotive but is suitable to use for many other embedded products
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Hans Nyström, Prevas
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15:00-15:30
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Functional Test Developing Under The Economic Crises without reducing testability
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Stig-Gunnar Jensen, Flextronics
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15:30-16:00
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Coffee Break / Exhibition
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16:00-17:00
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Session 3: Various Test Techniques 1
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Chairman: Artur Jutman
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16:00-16:30
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The Benefits of FPGA-Enabled Instruments In RF and Communications Test
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Johan Olsson, NI
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16:30-17:00
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News from Conferences
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Chairman: Artur Jutman
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17:00-17:25
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Fruits & Refreshments / Exhibition
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17:25-19:00
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Panel debate: “Will Test survive the economic crises and can we afford quality variations”
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Panel moderator: Birger Schneider
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20:00
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Dinner at Scandic Infra City Hotel
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22:30
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Social get-together in the Bar at Scandic Infra City
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Wednesday, December 2nd, 2009
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Time
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Titles
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Speakers or additional info
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9:00-9:30
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Invited Speaker
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Chairman: Knut Båtstoløkken
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9:00-9:30
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From Technology Trends To Requirements – New Views About Instruments
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Jyrki Sippola, NOKIA
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9:30-10:30
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Session 4: Boundary Scan 1
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Chairman: Stig-Gunnar Jensen
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9:30-10:00
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BS2VHDL and Other Embedded Techniques for BS Test Acceleration
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Artur Jutman, Tallinn University of Technology
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10:00-10:30
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Deployment of JTAG Based HW Self-Test in a Radio Base Station
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Thomas Kronqvist, SAAB
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10:30-11:00
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Coffee Break / Exhibition
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11:00-12:30
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Session 5: Boundary Scan 2
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Chairman: Bjørn B. Larsen
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11:00-11:30
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RAM testing with Boundary Scan - Structural Test or Functional Test?
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Jan Heiber, GOEPEL Electronic
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11:30-12:00
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Using Configurable Logic And Boundary Scan To Test Advanced Board Interface Protocols
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Anthony Sparks, JTAG Technologies
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12:00-12:30
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Non-Intrusive Board Test Strategies For The Intel Xeon Processor 5500 Series
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Kent Zetterberg, ASSET InterTech Inc
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12:30-13:30
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Lunch
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13:30-15:00
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Session 6: Various Test Techniques 2
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Chairman: Bengt Magnhagen
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13:30-14:00
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An (Almost) C-Testable Strategy For NoCs
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Kim Petersén, HDC
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14:00-14:30
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How To Optimize Your PXI Functional Test System combined JTAG Boundary Scan Technology
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Victor Fernandes, Geotest MTS
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14:30-15:00
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Acoustical Noise Problems in Production Test of Elektroacoustical Units and Electronic Cabinets
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Birger Schneider, NI
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15:00-15:15
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Closing Session: concluding remarks
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Knut Båtstoløkken
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